There are clock handoff circuits according to the related art which convert input data in synchronism with a certain clock into data in synchronism with a different clock and output the converted data. In a clock handoff circuit, a comparison is carried out between the phases of write addresses and read addresses of a readable/writable dual port RAM (random access memory) to control the write addresses and read addresses such that no conflict occurs between them.
For example, there are clock handoff circuits which control write addresses based on a write frame pulse signal and control read addresses based on a read frame pulse signal having a phase different from the phase of the write address pulse signal (for example, see JP-A-2004-140619 (Patent Document 1)).
There are clock handoff circuits which monitor the phases of write addresses and read addresses. When the phases approach each other to leave a predetermined distance between them, the write addresses and read addresses are initialized such that a certain distance kept between them (for example, see JP-A-2009-218885 (Patent Document 2)).
There are proposed optical signal transmission systems which perform a process of destuffing a high-order transmission frame by comparing the phases of write addresses and read addresses of an FIFO (first-in first-out) memory using a phase comparator of a PLL (phase-locked loop) circuit to control the write addresses and the read addresses appropriately (for example, see JP-A-2008-148250 (Patent Document 3)).